Logic circuits capable of gigabit per second operating rates are, for example, especially suitable in a computer that provides a real time computation of a Fourier transform and a fast multiplication of operands.
The computer typically has an arithmetic unit that includes a plurality of full adder circuits, each comprised of a group of two series coupled exclusive-OR gates. When signals are applied to inputs of a logic gate, a modulo 2 sum signal is provided at the output thereof after a time known as a gate delay. The gate delays of the group of gates determines the maximum operating rate of the arithmetic unit.
Prior art gates often include silicon bipolar "emitter-coupled logic" (ECL) devices that operate at many hundreds of megahertz. A circuit of LSI ECL gates, for example, typically exhibits a gate time delay of 0.5 nanoseconds. However, an experimental non-threshold logic circuit of ECL gates exhibited a 100 picosecond gate delay (T. Sakai, Y. Sunohara, N. Nakamura, and T. Sudo, "A 100 PS Bipolar Logic," Digest Tech. Papers, 1977, ISSCC, pp. 196-197).
Recently, gallium arsenide (GaAs) material has been used to make MESFET circuits that perform frequency division at four gigahertz. This was reported by R. Van Tuyl, C. Liechti, and C. Stolte in "Gallium Arsenide Digital Integrated Circuits," Tech. Report AFAL-TR-76-264, Air Force Systems Command, Wright-Patterson AFB, Ohio, April 1977. Alternatively, gigabit per second gates are made by using a GaAs transferred electron logic device (TELD). TELDs are more commonly known as Schottky-barrier-gate Gunn-effect digital devices.
The TELD may be used to construct simpler, faster gates for performing logic functions with few TELDs per logic function. Although the MESFET devices may be used to construct a gate, many MESFET devices are needed to build a gate that may be constructed with few TELDs.
A bias voltage is usually applied between the anode and the cathode of the TELD and a second bias voltage is applied between the gate and cathode, thereby causing a current to flow therethrough. The anode bias voltage is typically set to about 90% of a threshold voltage. When the anode to cathode voltage equals or exceeds the threshold voltage, a mobile "dipole" domain is created in the TELD. The dipole domain comprises an electron charge depletion region, preceding an electron charge accumulation region, that drifts from a gate terminal of the TELD to the anode during a portion of the transit time period. The transit time period is the total time for domain formation, drift to the anode and collection at the anode. The dipole domain causes a decrease in the TELD current during the domain formation time and continued lower current during drift portion of the transit time. During the collection time, the current increases. When the anode to cathode voltage is maintained in excess of the threshold voltage, domains are serially formed resulting in the above described current flow.
The reciprocal of the transit time period is the transit time frequency. In TELD devices utilized in resistive circuits, the transit time frequency depends strongly on the domain transit time which is proportional to domain velocity and inversely proportional to anode-to-gate (if a gate is not present, anode-to-cathode) separation. Thus, the transit time period of a set of TELDs made from GaAs material of similar properties can be tailored as desired by choice of the values of anode-to-gate separation.
It should be understood that the TELD has a negative resistance characteristic when the domain is formed. Accordingly, when a resistive load is in series with the TELD, a decrease in the current occurs concurrently with an increase in the anode to cathode voltage.
The anode-to-cathode threshold voltage is determined by the gate bias voltage with respect to the cathode, the TELD geometry and material constants. As the gate-to-cathode voltage increases the anode-to-cathode threshold voltage increases.
A split gate TELD has first and second gates substantially equi-distant from the anode. When the split gate TELD operates at a given anode-to-cathode bias voltage, as each gate to cathode voltage increases, the anode-to-cathode threshold voltage increases. When, for example, the first and second gates have a relatively positive bias voltage, a relatively high threshold voltage is established. When the first gate has a relatively positive bias voltage and the second gate has a relatively negative bias voltage, an intermediate threshold voltage is established. When the first and second gates have the relatively negative bias voltage, a relatively low threshold voltage is established. Because of the threshold voltage, the split gate TELD may be used to construct one type of circuit that performs a logical OR function and another type of circuit that performs a logical AND function. The design of logical OR and AND TELD circuits is described by S. Kataoka, N. Hashiyume, M. Kawashima, and Y. Komamiya in an article entitled "High Field Domain Function Logic Devices with Multiple Control Electrodes," Proc. 4th Bienn. Cornell Elec. Eng. Conf. vol. 4, pp. 225-234, 1973.